With the advantages of large transmission capacity, rapid and flexible power regulation, and non-synchronous networking, modular multilevel converter (MMC) high-voltage direct current (HVDC) systems play a growing role in long-distance transmission and grid interconnection. In such systems, dc-voltage regulation shapes both dc-bus stiffness and ac-side stability, and operating-point variation directly affects power-transfer capability. However, under dc-side disturbances and power changes, the cascaded proportional-integral (PI) dc-voltage loop suffers from slow response and poor stability. The energy-based full-state feedback linear control (FSFC) takes the squared dc-bus voltage as the outer state, recasting the nonlinear capacitor-energy dynamics as a linear plant and improving dynamic response and damping. However, its controller gain still depends on a plant gain that shifts with transferred power and arm capacitance.

Active disturbance rejection control (ADRC) with a linear extended state observer addresses this drift by lumping unmodelled dynamics into a total disturbance, yet its algebraic gain inversion destabilises the dc-voltage loop under input-gain deviations. Aiming at these issues, this article proposes a three-element dc-voltage controller. First, the FSFC energy-based formulation is retained so that the outer loop sees a linear capacitor-energy plant, while the d/q-current and circulating-current inner loops keep their feedback linearisation. Second, the algebraic gain inversion of conventional ADRC is replaced by a first-order dynamic-inversion channel that recovers closed-loop stability. Third, a residual observer is cascaded with the primary extended state observer for hierarchical disturbance compensation without bandwidth escalation. The input gain is identified online from the modal residue of the open-loop integrator eigenvalue, adapting to the operating point.

The controllers are compared on a 1000 MVA, 640 kV point-to-point MMC-HVDC benchmark with short-circuit ratio of five, 500 MW steady-state power flow, and a 10% (50 MW) active-power reference step at the sending-end terminal. In the frequency domain, the proposed controller provides 20 to 30 dB of additional low-frequency attenuation over FSFC and 30 to 40 dB over PI, and removes the approximately 3 Hz resonance peak of the PI baseline. In the time domain, it yields smaller oscillation, a lower peak dc-bus voltage deviation (0.47 kV vs 1.04 kV for FSFC, 5.17 kV for PI), and shorter settling time, while active-power tracking is comparable.

The results show that dynamic inversion is essential when the ADRC input gain is operating-point-dependent, and the cascaded observer adds disturbance rejection without bandwidth escalation. A nonlinear adaptive-gain extension is left for future work.